When interconnecting an plurality of power semiconductor switching devices such as metal oxide semiconductor controlled thyristors (MCT's), insulated gate bipolar transistors (IGBT's), or metal oxide semiconductor field effect transistors (MOSFET's), it is important to minimize inequalities among the interconnected devices with respect to heat dissipation, power sharing and a variety of thermally influenced performance characteristics, as well as signal distortion. More specifically, it is important to minimize differential voltages between the anodes of the power semiconductor switching devices when said devices are paralleled at switch-on, switch-off and steady state conditions; to equalize the electrical impedances between the anodes and cathodes of the paralleled devices; and to optimize current sharing between the paralleled devices during switch-on, switch-off and steady state conditions.
Accordingly, it is the object of the present invention to arrange the plurality of power semiconductor switching devices to minimize interconnecting lead lengths to insure the aforementioned results.